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datasheet 2 output pcie ge n1/2 synthesizer idt5v41065 idt? 2 output pcie gen1/2 synthesizer 1 idt5v41065 rev e 112111 recommended applications 2 output synthesizer for pcie gen1/2 and ethernet general description the idt5v41065 is a pcie gen2 compliant spread spectrum capable clock generator. the device has 2 differential hcsl outputs and can be used in communication or embedded systems to subtantially reduce electro-magnetic interference (emi). the spread amount and output frequency are selectable via select pins. the idt5v41065 can also supply 25 mhz, 125 mhz and 200 mhz outputs for applications such as ethernet. output features ? 2 - 0.7v current mode differential hcsl output pairs features/benefits ? 16-pin tssop package; small board footprint ? spread-spectrum capable; reduces emi ? outputs can be terminated to lvds; can drive a wider variety of devices ? 25 mhz, 125 mhz and 200 mhz output frequencies; supports ethernet applications ? oe control pin; greater system power management ? spread% and frequency pin selection; no software required to configure device ? industrial temperature range available; supports demanding embedded applications ? for pcie gen3 applications, see the 5v41235 key specifications ? cycle-to-cycle jitter < 100 ps ? output-to-output skew < 50 ps ? pcie gen2 phase jitter < 3.0ps rms block diagram phase lock loop clock buffer/ crystal oscillator vdd gnd x1/iclk x2 25 mhz crystal or clock control logic ss1:ss0 2 s1:s0 2 clk0 clk0 rr(iref) clk1 clk1 2 2 oe optional tuning crystal capacitors
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 2 idt5v41065 rev e 112111 pin assignment output select table 1 (mhz) spread selection table 2 pin descriptions 1 2 3 x2 4 s1 5 6 clk0 7 8 clk0 gndoda vddxd oe ss0 16 x1/iclk ss1 clk1 vddoda 15 14 13 12 11 10 9 16-pin (173 mil) tssop gndxd s0 iref clk1 s1 s0 clk(1:0), clk(1:0) 00 25m 0 1 100m 1 0 125m 1 1 200m ss1 ss0 spread% 00 no spread 0 1 down -0.5 1 0 down -0.75 11 no spread pin number pin name pin type pin description 1 s0 input select pin 0. see table1. internal pull-up resistor. 2 s1 input select pin 1. see table 1. internal pull-up resistor. 3 ss0 input spread select pin 0. see table 2. internal pull-up resistor. 4 x1/iclk input crystal or clock input. connect to a 25 mhz crystal or single ended clock. 5 x2 output crystal connection. leave unconnected for clock input. 6 oe input output enable. tri-states outputs and device is not shut down. internal pull-up resistor. 7 gndxd power connect to ground. 8 ss1 input spread select pin 1. see table 2. internal pull-up resistor. 9 iref output precision resistor attached to this pin is connected to the internal current reference. 10 clk1 output hcsl complementary clock output 1. 11 clk1 output hcsl true clock output 1. 12 vddoda power connect to voltage supply +3.3 v for output driver and analog circuits 13 gndoda power connect to ground. 14 clk0 output hcsl complementary clock output 0. 15 clk0 output hcsl true clock output 0. 16 vddxd power connect to voltage supply +3.3 v for crystal oscillator and digital circuit.
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 3 idt5v41065 rev e 112111 applications information external components a minimum number of external components are required for proper operation. decoupling capacitors decoupling capacitors of 0.01 f should be connected between each vdd pin and the ground plane, as close to the vdd pin as possible. do not share ground vias between components. route power from power source through the capacitor pad and then into ics pin. crystal a 25 mhz fundamental mode parallel resonant crystal should be used. this crystal must have less than 300 ppm of error across temperature in order for the idt5v41065 to meet pci express specifications. crystal capacitors crystal capacitors are connected from pins x1 to ground and x2 to ground to optimize the accuracy of the output frequency. c l = crystal?s load capacitance in pf crystal capacitors (pf) = (c l - 8) * 2 for example, for a crystal with a 16 pf load cap, each external crystal cap would be 16 pf. (16-8)*2=16. current source (iref) reference resistor - r r if board target trace impedance (z) is 50 , then r r = 475 (1%), providing iref of 2.32 ma. the output current (i oh ) is equal to 6*iref. output termination the pci-express differential clock outputs of the idt5v41065 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. the idt5v41065 can also be configured for lvds compatible voltage levels. see the lvds compatible layout guidelines section. output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the idt5v41065.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see output termination sections - pages 3 ~ 5
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 4 idt5v41065 rev e 112111 layout guidelines common r ecommendations for differential routing d imension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 5 idt5v41065 rev e 112111 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 6 idt5v41065 rev e 112111 typical pci-express (hcsl) waveform typical lvds waveform 0.175 v 0.525 v 0.175 v 0.525 v t or t of 500 ps 500 ps 700 mv 0 1150 mv 1250 mv t or t of 500 ps 500 ps 1325 mv 1000 mv 1150 mv 1250 mv
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 7 idt5v41065 rev e 112111 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the idt5v41065. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificat ions is not implied. exposure to ab solute maximum rating conditions for extended periods can affect product reliability. electrical parameters are gua ranteed only over the recommended operating temperature range. dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c 1. single edge is monotonic when transitioning through region. 2. inputs with pull-ups/-downs are not included. item rating supply voltage, vddxd, vddoda 4.6 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c esd protection (input) 2000 v min. (hbm) parameter symbol conditions min. typ. max. units supply voltage v 3.135 3.3 3.465 v input high voltage 1 v ih s0, s1, oe, iclk, ss0, ss1 2.2 vdd +0.3 v input low voltage 1 v il s0, s1, oe, iclk, ss0, ss1 vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd -5 5 a operating supply current @100 mhz i dd r s =33 , r p =50 , c l =2 pf 63 85 ma i ddoe oe =low 42 50 ma input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf x1, x2 capacitance c inx 5pf pin inductance l pin 5nh output impedance z o clk outputs 3.0 k pull-up resistor r pu s0, s1, oe, ss0, ss1 100 k
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 8 idt5v41065 rev e 112111 ac electrical characterist ics - clk0/clk1, clk0/clk1 unless stated otherwise, vdd=3.3 v 5% , ambient temperature -40 to +85 c note 1: test setup is r s =33 , r p =50 with c l =2 pf, rr = 475 (1%). note 2: measurement taken from a single-ended waveform. note 3: measurement taken from a differential waveform. note 4: measured at the crossing point where instantaneous voltages of both clk and clk are equal. note 5: clk pins are tri-stated when oe is low as serted. clk is driven diff erential when oe is high. electrical characteristics - differential phase jitter note 1. guaranteed by design and characterization, not 100% tested in production. note 2. see http://www.pcisig.com for complete specs. note 3: applies to 100mhz, spread off and 0.5% down spread only. parameter symbol conditions min. typ. max. units input frequency 25 mhz output frequency hcsl termination 25 200 mhz lvds termination 25 100 mhz output high voltage 1,2 v oh hcsl 850 mv output low voltage 1,2 v ol hcsl -150 mv crossing point voltage 1,2 absolute 250 550 mv crossing point voltage 1,2,4 variation over all edges 140 mv jitter, cycle-to-cycle 1,3 100 ps frequency synthesis error all outputs 0 ppm modulation frequency spread spectrum 30 32.9 33 khz rise time 1,2 t or from 0.175 v to 0.525 v 175 700 ps fall time 1,2 t of from 0.525 v to 0.175 v 175 700 ps rise/fall time variation 1,2 125 ps output to output skew 50 ps duty cycle 1,3 45 55 % output enable time 5 all outputs 50 100 ns output disable time 5 all outputs 50 100 ns stabilization time t stable from power-up vdd=3.3 v 1.8 ms spread spectrum transition time t spread stabilization time after spread spectrum changes 730ms parameter symbol conditions min typ max units notes jitter, phase t jphasepll pcie gen1 32 86 ps (p-p) 1,2,3 t jphaselo pcie gen2, 10 khz < f < 1.5 mhz 0.8 3 ps (rms) 1,2,3 t jphasehigh pcie gen2, 1.5 mhz < f < nyquist (50 mhz) 2.3 3.1 ps (rms) 1,2,3
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 9 idt5v41065 rev e 112111 thermal characteristics marking diagram (5V41065PGG) marking diagram (5V41065PGGi) notes: 1. line 1 and 2: idt part number. 2. line 3: # ? die revision; yyww ? date code; $ ? assembly location. 3. ?g? after the two-letter package code designates rohs compliant package. 4. ?i? at the end of part number indicates industrial temperature range. 5. bottom marking: country of origin if not usa. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w 1 8 9 16 idt5v410 65pgg #yyww$ 1 8 9 16 idt5v410 65pggi #yyww$
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 10 idt5v41065 rev e 112111 package outline and package dimensions (16-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information ?g? after the two-letter package code are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 5V41065PGG see page 8 tubes 16-pin tssop 0 to +70 c 5V41065PGG8 tape and reel 16-pin tssop 0 to +70 c 5V41065PGGi see page 8 tubes 16-pin tssop -40 to +85 c 5V41065PGGi8 tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches* symbol min max min max a -- 1.20 -- 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 a0 8 0 8 aaa -- 0.10 -- 0.004
idt5v41065 2 output pcie gen1/2 synthesizer idt? 2 output pcie gen1/2 synthesizer 11 idt5v41065 rev e 112111 revision history rev. originator date description of change a 07/15/08 new datasheet; pr eliminary initial release. b rdw 01/13/10 added gen2 to title; update electrical tabl es per char; added differential phase jitter table. c rdw 04/27/10 updated electrical tables per char ; vdd is now 3.3 5%; released to final. d rdw 07/19/10 1. updated title and general decription 2. updated cycle-to-cycle jitter spec from 125 to 100 ps. e rdw 11/21/11 1. changed title to ?2 output pcie gen1/2 synthesizer? 2. added note to features section: ?for pcie gen3 applications, see 5v41235? 3. updated differential phase jitter table.
? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com idt5v41065 2 output pcie gen1/2 synthesizer

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